RhinoPower Ltd

This is my script for the H8_536 processor used in a number of Suzuki ECUs, including US OBD2 models. This script names CPU registers and intterupt vectors and uses the interrupt vectors to performs code disassembly.

For some reason I can't link to the file so here it is in full:

[code]

// H8_536.idc
// RhinoPower Ltd
// 7th March 2012
// Names interrupt vectors and disassembles the code pointed to by them
// Names registers
// Does not name interrupt service routines because these could by called from more than one place (ie start address is often defined for all unused interrupts)
// http://www.rhinopower.org

#include <idc.idc>

static main()
{
 
 auto i;
 auto codestart;
 
// define all vectors
// and seek out code

 for(i=0;i<256;i=i+2){ MakeWord(i); } // they are all 16-bit so do that first

 
 MakeNameEx(0,"RESET",0);
 codestart = Word(0);
 MakeCode(codestart);
 
 MakeNameEx(0x16,"NMI",0);
 codestart = Word(0x16);
 MakeCode(codestart);

 MakeNameEx(0x40,"IRQ0",0);
 codestart = Word(0x40);
 MakeCode(codestart);

 MakeNameEx(0x42,"IRQ1",0);
 codestart = Word(0x42);
 MakeCode(codestart);

 MakeNameEx(0x50,"IRQ2",0);
 codestart = Word(0x50);
 MakeCode(codestart);

 MakeNameEx(0x52,"IRQ3",0);
 codestart = Word(0x52);
 MakeCode(codestart);

 MakeNameEx(0x60,"FRT1_ICI",0);
 codestart = Word(0x60);
 MakeCode(codestart);

 MakeNameEx(0x62,"FRT1_OCIA",0);
 codestart = Word(0x62);
 MakeCode(codestart);

 MakeNameEx(0x64,"FRT1_OCIB",0);
 codestart = Word(0x64);
 MakeCode(codestart);

 MakeNameEx(0x66,"FRT1_FOVI",0);
 codestart = Word(0x66);
 MakeCode(codestart);

 MakeNameEx(0x68,"FRT2_ICI",0);
 codestart = Word(0x68);
 MakeCode(codestart);

 MakeNameEx(0x6A,"FRT2_OCIA",0);
 codestart = Word(0x6A);
 MakeCode(codestart);

 MakeNameEx(0x6C,"FRT2_OCIB",0);
 codestart = Word(0x6C);
 MakeCode(codestart);

 MakeNameEx(0x6E,"FRT2_FOVI",0);
 codestart = Word(0x6E);
 MakeCode(codestart);

 MakeNameEx(0x70,"FRT3_ICI",0);
 codestart = Word(0x70);
 MakeCode(codestart);

 MakeNameEx(0x72,"FRT3_OCIA",0);
 codestart = Word(0x72);
 MakeCode(codestart);

 MakeNameEx(0x74,"FRT3_OCIB",0);
 codestart = Word(0x74);
 MakeCode(codestart);

 MakeNameEx(0x76,"FRT3_FOVI",0);
 codestart = Word(0x76);
 MakeCode(codestart);

 MakeNameEx(0x78,"CMIA",0);
 codestart = Word(0x78);
 MakeCode(codestart);

 MakeNameEx(0x7A,"CMIB",0);
 codestart = Word(0x7A);
 MakeCode(codestart);

 MakeNameEx(0x7C,"OVI",0);
 codestart = Word(0x7C);
 MakeCode(codestart);
 
 MakeNameEx(0x80,"SCI1_ERI",0);
 codestart = Word(0x80);
 MakeCode(codestart);

 MakeNameEx(0x82,"SCI1_RXI",0);
 codestart = Word(0x82);
 MakeCode(codestart);

 MakeNameEx(0x84,"SCI1_TXI",0);
 codestart = Word(0x84);
 MakeCode(codestart);

 MakeNameEx(0x88,"SCI2_ERI",0);
 codestart = Word(0x88);
 MakeCode(codestart);

 MakeNameEx(0x8A,"SCI2_RXI",0);
 codestart = Word(0x8A);
 MakeCode(codestart);

 MakeNameEx(0x8C,"SCI2_TXI",0);
 codestart = Word(0x8C);
 MakeCode(codestart);

 MakeNameEx(0x90,"ADI",0);
 codestart = Word(0x90);
 MakeCode(codestart);

// define all registers - these are all 8 bits but a word access is often used so make them all 8-bits

 for(i=0xFE80;i<0x10000;i=i+1){ MakeByte(i); } // they are all 8-bit so do that first

 //PORTS (PORT 9 BELOW)
 MakeNameEx(0xFE80,"P1DDR",0);
 MakeNameEx(0xFE81,"P2DDR",0);
 MakeNameEx(0xFE82,"P1DR",0);
 MakeNameEx(0xFE83,"P2DR",0);
 MakeNameEx(0xFE84,"P3DDR",0);
 MakeNameEx(0xFE85,"P4DDR",0);
 MakeNameEx(0xFE86,"P3DR",0);
 MakeNameEx(0xFE87,"P4DR",0);
 MakeNameEx(0xFE88,"P5DDR",0);
 MakeNameEx(0xFE89,"P6DDR",0);
 MakeNameEx(0xFE8A,"P5DR",0);
 MakeNameEx(0xFE8B,"P6DR",0);
 MakeNameEx(0xFE8C,"P7DDR",0);

 MakeNameEx(0xFE8E,"P7DR",0);
 MakeNameEx(0xFE8F,"P8DR",0);

 //FRT1
 MakeNameEx(0xFE90,"FRT1_TCR",0);
 MakeNameEx(0xFE91,"FRT1_TCSR",0);
 MakeNameEx(0xFE92,"FRT1_FRCH",0);
 MakeNameEx(0xFE93,"FRT1_FRCL",0);
 MakeNameEx(0xFE94,"FRT1_OCRAF",0);
 MakeNameEx(0xFE95,"FRT1_OCRAL",0);
 MakeNameEx(0xFE96,"FRT1_OCRBH",0);
 MakeNameEx(0xFE97,"FRT1_OCRBL",0);
 MakeNameEx(0xFE98,"FRT1_ICRH",0);
 MakeNameEx(0xFE99,"FRT1_ICRL",0);

 //FRT2
 MakeNameEx(0xFEA0,"FRT2_TCR",0);
 MakeNameEx(0xFEA1,"FRT2_TCSR",0);
 MakeNameEx(0xFEA2,"FRT2_FRCH",0);
 MakeNameEx(0xFEA3,"FRT2_FRCL",0);
 MakeNameEx(0xFEA4,"FRT2_OCRAF",0);
 MakeNameEx(0xFEA5,"FRT2_OCRAL",0);
 MakeNameEx(0xFEA6,"FRT2_OCRBH",0);
 MakeNameEx(0xFEA7,"FRT2_OCRBL",0);
 MakeNameEx(0xFEA8,"FRT2_ICRH",0);
 MakeNameEx(0xFEA9,"FRT2_ICRL",0);

 //FRT3
 MakeNameEx(0xFEB0,"FRT3_TCR",0);
 MakeNameEx(0xFEB1,"FRT3_TCSR",0);
 MakeNameEx(0xFEB2,"FRT3_FRCH",0);
 MakeNameEx(0xFEB3,"FRT3_FRCL",0);
 MakeNameEx(0xFEB4,"FRT3_OCRAF",0);
 MakeNameEx(0xFEB5,"FRT3_OCRAL",0);
 MakeNameEx(0xFEB6,"FRT3_OCRBH",0);
 MakeNameEx(0xFEB7,"FRT3_OCRBL",0);
 MakeNameEx(0xFEB8,"FRT3_ICRH",0);
 MakeNameEx(0xFEB9,"FRT3_ICRL",0);

 //PWM
 MakeNameEx(0xFEC0,"PWM1_TCR",0);
 MakeNameEx(0xFEC1,"PWM1_DTR",0);
 MakeNameEx(0xFEC2,"PWM1_TCNT",0);

 MakeNameEx(0xFEC8,"PWM2_TCR",0);
 MakeNameEx(0xFEC9,"PWM2_DTR",0);
 MakeNameEx(0xFECA,"PWM2_TCNT",0);

 MakeNameEx(0xFED0,"PWM3_TCR",0);
 MakeNameEx(0xFED1,"PWM3_DTR",0);
 MakeNameEx(0xFED2,"PWM3_TCNT",0);

 //SCI1
 MakeNameEx(0xFED8,"SCI1_SMR",0);
 MakeNameEx(0xFED9,"SCI1_BRR",0);
 MakeNameEx(0xFEDA,"SCI1_SCR",0);
 MakeNameEx(0xFEDB,"SCI1_TDR",0);
 MakeNameEx(0xFEDC,"SCI1_SSR",0);
 MakeNameEx(0xFEDD,"SCI1_RDR",0);

 //ADC
 MakeNameEx(0xFEE0,"ADDRAH",0);
 MakeNameEx(0xFEE1,"ADDRAL",0);
 MakeNameEx(0xFEE2,"ADDRBH",0);
 MakeNameEx(0xFEE3,"ADDRBL",0);
 MakeNameEx(0xFEE4,"ADDRCH",0);
 MakeNameEx(0xFEE5,"ADDRCL",0);
 MakeNameEx(0xFEE6,"ADDRDH",0);
 MakeNameEx(0xFEE7,"ADDRDL",0);
 MakeNameEx(0xFEE8,"ADCSR",0);

 //WDT
 MakeNameEx(0xFEEC,"WDT_TCSR",0);
 MakeNameEx(0xFEED,"WDT_TCNT",0);

 //SCI2
 MakeNameEx(0xFEF0,"SCI2_SMR",0);
 MakeNameEx(0xFEF1,"SCI2_BRR",0);
 MakeNameEx(0xFEF2,"SCI2_SCR",0);
 MakeNameEx(0xFEF3,"SCI2_TDR",0);
 MakeNameEx(0xFEF4,"SCI2_SSR",0);
 MakeNameEx(0xFEF5,"SCI2_RDR",0);

 //SYSCR
 MakeNameEx(0xFEFC,"SYSCR1",0);
 MakeNameEx(0xFEFD,"SYSCR2",0);
 

 //PORT9
 MakeNameEx(0xFEFE,"P9DDR",0);
 MakeNameEx(0xFEFF,"P9DR",0);
 
 //INTC
 MakeNameEx(0xFF00,"INTC_IPRA",0);
 MakeNameEx(0xFF01,"INTC_IPRB",0);
 MakeNameEx(0xFF02,"INTC_IPRC",0);
 MakeNameEx(0xFF03,"INTC_IPRD",0);
 MakeNameEx(0xFF04,"INTC_IPRE",0);
 MakeNameEx(0xFF05,"INTC_IPRF",0);

 MakeNameEx(0xFF08,"INTC_DTEA",0);
 MakeNameEx(0xFF09,"INTC_DTEB",0);
 MakeNameEx(0xFF0A,"INTC_DTEC",0);
 MakeNameEx(0xFF0B,"INTC_DTED",0);
 MakeNameEx(0xFF0C,"INTC_DTEE",0);
 MakeNameEx(0xFF0D,"INTC_DTEF",0);
 
 
 //WSC
 MakeNameEx(0xFF10,"WSC",0);

 //RAM
 MakeNameEx(0xFF11,"RAMCR",0);

 //?
 MakeNameEx(0xFF12,"MDCR",0);
 MakeNameEx(0xFF13,"SBYCR",0);
 MakeNameEx(0xFF14,"WCR",0);
 MakeNameEx(0xFF15,"RSTCSR",0);

}

[/code]